ELPM-S3LW / Power architecture
Hardware power latch vs deep sleep.
How we prepare and verify this contentDeep sleep reduces consumption while keeping part of the system powered. A hardware power latch instead opens the main supply rails. In nodes that wake infrequently, removing the waiting current can matter more than optimizing a few milliseconds of processing.
Sleeping is not the same as being off.
In a conventional microcontroller, deep sleep stops the CPU and peripherals but keeps the domains required to retain state or recognize a wake source powered. The resulting current depends on the chip, its configuration and, critically, everything else still connected on the board.
A power latch works upstream. Once sensing, processing and transmission are complete, firmware releases the latch and physically interrupts the main rails. What remains is not the SoC sleep current, but leakage through the shutdown circuit and any wake sources deliberately left active.
| Aspect | Deep sleep | Hardware power latch |
|---|---|---|
| Main supply | Partially active | Physically interrupted |
| RAM/SoC state | Can be retained | Lost on restart |
| Startup | Resume from sleep | Full boot |
| Waiting current | Depends on SoC and board | Depends on latch and wake source |
Something still has to listen.
A fully unpowered node cannot wake itself. The design must keep at least one path active: an extreme low-power RTC, an edge detector, a sensor interrupt output or an external command.
ELPM-S3LW exposes gate, wake and force-on inputs and can schedule wake-up with an RV-3028-C7 RTC. Its datasheet specifies 45–100 nA for the RTC and 1–30 nA for the detecting inputs; with the RTC disabled, module deep stop is specified below 1 nA.
System boundary matters. These figures describe the module under the datasheet conditions. Battery, regulators, sensors, protection devices and carrier-board layout can dominate the complete product's measured current.
Time in each state determines the budget.
Average consumption is not the lowest number in a table. It is the energy used during boot, sensing, processing, transmission and waiting, divided by the complete cycle time.
Iavg = (Iactive × tactive + Iwait × twait) / (tactive + twait)
If the node transmits every few seconds, a longer boot can erase the power-latch advantage. If it transmits only a few times per day, waiting occupies almost the whole cycle and waiting current becomes the dominant parameter.
When to choose each approach.
Deep sleep fits when
- wake-ups are frequent or latency must be minimal;
- state must remain in RAM;
- external peripherals dominate consumption anyway;
- the achieved waiting current already meets the budget.
A power latch fits when
- the node remains inactive for hours or days;
- an event or RTC can start the complete system;
- firmware can restart deterministically on every cycle;
- battery or energy harvesting makes every continuous current significant.
Measure the system, not just the component.
OBJEX LABS publishes the Otii recordings used to characterize ELPM-S3LW deep stop, RTC, LoRa and Wi-Fi behavior. They are bench data for checking waveforms and building a model, not an automatic battery-life promise for a different product.
A real design must be measured as a complete board and account for temperature, battery self-discharge, regulator efficiency, radio profile and safety margin.
Review ELPM-S3LW specifications, datasheet and raw power traces.
Explore ELPM-S3LW